PCI-Express 5.0 Motherboard - Chipset Intel Z690

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 Alder Lake - modular approach Intel's 12th, 13th and possibly 14th generation of processors, code names; Alder Lake, Raptor Lake and Meteor Lake, bringing a new design philosophy which diverges significantly from previous processor design. Reminiscent of system-on-chips (SoC) of smartphones, it features not just one, but two core architectures linked together using new scalable technology of packing electronic modules into the chip. It will feature up to 16-cores split between at most eight Golden Cove performance cores (P-cores), and eight Gracemont efficiency cores (E-cores) organized in two 4-core modules.

That is hybrid architecture which allows for the use of two types of CPU cores in one package: big-performance cores for heavy tasks and small-efficient cores for everything else. Improved and varied cores is only half the success of this CPU. It is important way to coordinate how these two types of core are working together. Perform of this role is by Thread Director. The end result is about 20% faster and 50% - 80% more efficient CPU than its predecessors. Gracemont is the architecture name for Intel's efficiency cores. It features an overhauled architecture with a deeper frontend, wider backend, and will be built on the 'Intel 7 node', bunch of products known as SuperFin 10 nm, 10 nm+, 10 nm++ i 10 nm+++. As the Figure shows at beginning of this paragraph, scalable architecture use the same electronic 'packages', arranged differently to create processors for desktop, mobile and ultra-mobile devices. To to ensure the above new LGA 1700 socket for desktop PC is used.

Alder Lake also features up to 30 MB of cache, 16 lanes of PCIe 5, and DDR5 as well as DDR4 memory support and Tiger Lake's Xe LP graphics ported to the 'Intel 7 node'. Alder Lake uses three fabrics to link all its parts together and fine-tune power consumption. The path between the compute cores, graphics, last-level cache (LLC / L3) and working memory is the compute fabric, which can operate at 1 TB/s. The input/output (I/O) fabric, which operates at 64 GB/s, passes data between I/Os and internal devices. And lastly, the memory fabric operates at 204 GB/s and can dynamically adjust the bus width and frequency for multiple operating points. Having multiple dynamically scaling fabrics allows Alder Lake to more efficiently direct power to where it's needed the most. Branch prediction is a critical feature in modern CPUs. It predicts what instructions are needed next before a program even requests them, thereby reducing CPU wait times and wasted instructions. Many of the CPU processing stages depend on accurate branch predictions; for example, if there's a mispredict, then the instructions stored in the out-of-order buffer may need to be flushed. Gracemont has a 5'000 entry-long branch target cache for its history-based branch prediction to help generate accurate instruction pointers, reducing the chances of mispredicts.

In addition to cutting wait time, Gracemont carries a 64 KB + 32 KB of cache. Instruction cache of 64 KB stores the most frequently used instructions close at hand, as well as Intel's first 'on-demand instruction length decoder' that decodes new code quickly. Cache of 32 KB is for data. The main instruction decoder got an upgrade too. It can now decode up to six instructions per cycle while maintaining the efficiency of a much narrower core. The decoder, which translates opcode into micro-ops, is important in keeping the backend fed at all times so the processor achieves maximum efficiency; being able to decode more instructions per clock is of course better for overall performance. The decoders are aided by a new hardware-driven load balancer. Instead of dumping a long chain of sequential instructions onto a few decoders, load balancers break them up into smaller segments and distribute them across all of the decoders, increasing parallelism. Further down the process flow are the data Execution Units (EU). The integer EU ports are complemented by dual-energy multipliers and dividers.

The single-instruction, multiple-data (SIMD) arithmetic logic units (ALUs) in the vector operations now support Intel's virtual Neural Network Instructions (VNNI). Two floating-point pipelines allow the execution of two independent add or multiply operations, as well as two multiply-add instructions per cycle thanks to new vector extension instructions. Gracemont's vector stack also comes with cryptography units that provide AES and SHA acceleration, allowing it to offload the encryption workloads in security-sensitive applications. Finally, there's the memory subsystem. Two load and two store pipelines that enable 32 bytes read and write simultaneously. The L2 cache size is configurable between 2 and 4 MB. In a core-on-core comparison, Gracemont delivers 40% more performance at the same power as Skylake, and delivers the same performance using 40% less power. This means that Gracemont is around 2.5 times more efficient in single-core scenarios. In a four-core configuration, Gracemont delivered 80% more performance than two Skylake cores running four threads while still consuming less power. The program properties are taken care by Thread Director, which still accounts for thermals, operating conditions, and power limits. It also picks out threads that need the most performance so it can assign them to the P-cores. Similarly, it delegates background tasks to the E-cores, and threads to P-cores. Everything is dynamic, based on the tasks at hand, and is fully autonomous. But that doesn't mean Thread Director locks heavy workloads exclusively to P-cores. It will take advantage of any idle cores if there are resources available. In a heavy multithreaded workload, Thread Director will distribute the workload across all P-cores and E-cores.

So, the main features of Alder Lake, Raptor Lake and Meteor Lake processors are shown in next Figure:

 Alder, Raptor, Meteor main features  PI Network
Figure 3.5.55 Main features of LGA 1700 processors.  

The short description in the Figure above is in a way a continuation of the 'Tick-Tock' Figure which encompasses all previous Intel technologies. Look at what Intel's 'z690' series of chipset offers.

Example XVII

In this example shown in the block diagram of the chipset z690. Shown in the example motherboard supports Core i3, Core i5, Core i7 and Core i9 microprocessors of twelfth , thirteenth and fourteenth generation planned with the socket LGA 1700.

Along with the new set of processors, motherboard vendors will be launching a variety of 600-series chipset based motherboards for Alder Lake, and these motherboards will suppot three generations of mikroprocessors, which is for customer very convenient.

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Quite a lot of data about the new generations of microprocessors and their associated chipset has not yet been published, and the data listed on this page may not be accurate. Over time, the data will be corrected and the page will be supplemented with an example of a single motherboard.


  Citing of this page:
Radic, Drago. " IT - Informatics Alphabet " Split-Croatia.
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